Bambino-200 Manual/Hardware
From Manuals
The following image shows where some of the hardware components are located.
Contents |
Microcontroller
The Bambino 200 includes a NXP LPC4330 microcontroller. These dual core 32-bit ARM Cortex-M4/M0 RISC microcontroller are capable of 204-MHz operation with a Thumb2 instruction set for smaller object code. It uses a Harvard architecture with separate local instruction and data buses as well as a separate peripherals bus. Please see NXP’s LPC4330 Microcontroller's User Manual for more information and register definitions.
LPC4330 key features
- Cortex-M4 Processor core
- Built-in Memory Protection Unit (MPU) supporting eight regions.
- Running at frequencies of up to 204 MHz.
- Built-in Nested Vectored Interrupt Controller (NVIC).
- Hardware floating-point unit.
- Non-maskable Interrupt (NMI) input.
- JTAG and Serial Wire Debug (SWD), serial trace, eight breakpoints, and four watch points.
- Enhanced Trace Module (ETM) and Enhanced Trace Buffer (ETB) support.
- System tick timer.
- Cortex-M0 Processor core
- Running at frequencies of up to 204 MHz.
- JTAG and built-in NVIC.
- On-chip memory
- 264 kB SRAM for code and data use.
- Multiple SRAM blocks with separate bus access. Two SRAM blocks can be powered down individually.
- 64 kB ROM containing boot code and on-chip software drivers.
- 128 bit general-purpose One-Time Programmable (OTP) memory.
- Clock generation unit
- Crystal oscillator with an operating range of 1 MHz to 25 MHz.
- 12 MHz Internal RC (IRC) oscillator trimmed to 1 % accuracy over temperature and voltage.
- Ultra-low power Real-Time Clock (RTC) crystal oscillator.
- Three PLLs allow CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. The second PLL is dedicated to the High-speed USB, the third PLL can be used as audio PLL.
- Clock output.
- Configurable digital peripherals
- Serial GPIO (SGPIO) interface.
- State Configurable Timer (SCT) subsystem on AHB.
- Global Input Multiplexer Array (GIMA) allows to cross-connect multiple inputs and outputs to event driven peripherals like the timers, SCT, and ADC0/1.
- Serial interfaces
- Quad SPI Flash Interface (SPIFI) with 1-, 2-, or 4-bit data at rates of up to 52 MB per second.
- 10/100T Ethernet MAC with RMII and MII interfaces and DMA support for high throughput at low CPU load. Support for IEEE 1588 time stamping/advanced time stamping (IEEE 1588-2008 v2).
- One High-speed USB 2.0 Host/Device/OTG interface with DMA support and on-chip high-speed PHY (USB0).
- One High-speed USB 2.0 Host/Device interface with DMA support, on-chip full-speed PHY and ULPI interface to external high-speed PHY (USB1).
- USB interface electrical test software included in ROM USB stack.
- Four 550 UARTs with DMA support: one UART with full modem interface; one UART with IrDA interface; three USARTs support UART synchronous mode and a smart card interface conforming to ISO7816 specification.
- Up to two C_CAN 2.0B controllers with one channel each.
- Two SSP controllers with DMA, FIFO and multi-protocol support.
- One SPI controller.
- One Fast-mode Plus I2C-bus interface with monitor mode and with open-drain I/O pins conforming to the full I2C-bus specification. Supports data rates of up to 1 Mbit/s.
- One standard I2C-bus interface with monitor mode and with standard I/O pins.
- Two I2S interfaces, each with DMA support and with one input and one output.
- Digital peripherals
- External Memory Controller (EMC) supporting external SRAM, ROM, NOR flash, and SDRAM devices.
- Secure Digital Input Output (SD/MMC) card interface.
- Eight-channel General-Purpose DMA controller can access all memories on the AHB and all DMA-capable AHB slaves.
- General-Purpose Input/Output (GPIO) pins with configurable pull-up/pull-down resistors.
- GPIO registers are located on the AHB for fast access. GPIO ports have DMA support.
- Up to eight GPIO pins can be selected from all GPIO pins as edge and level sensitive interrupt sources.
- Two GPIO group interrupt modules enable an interrupt based on a programmable pattern of input states of a group of GPIO pins.
- Four general-purpose timer/counters with capture and match capabilities.
- One motor control Pulse Width Modulator (PWM) for three-phase motor control.
- One Quadrature Encoder Interface (QEI).
- Repetitive Interrupt timer (RI timer).
- Windowed watchdog timer (WWDT).
- Ultra-low power Real-Time Clock (RTC) on separate power domain with 256 bytes of battery powered backup registers.
- Alarm timer; can be battery powered.
- Analog peripherals
- One 10-bit DAC with DMA support and a data conversion rate of 400 kSamples/s.
- Two 10-bit ADCs with DMA support and a data conversion rate of 400 kSamples/s. Up to eight input channels per ADC.
- Unique ID for each device.
- Power
- Single 3.3 V (2.2 V to 3.6 V) power supply with on-chip internal voltage regulator for the core supply and the RTC power domain.
- RTC power domain can be powered separately by a 3 V battery supply.
- Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down.
- Processor wake-up from Sleep mode via wake-up interrupts from various peripherals.
- Wake-up from Deep-sleep, Power-down, and Deep power-down modes via external interrupts and interrupts generated by battery powered blocks in the RTC power domain.
- Brownout detect with four separate thresholds for interrupt and forced reset.
- Power-On Reset (POR).
LPC4330 Block Diagram
LPC4330 Memory Map
Serial Flash Memory
The Bambino 200 uses Quad SPI Flash for it's program and non-volatile data storage. The quad SPI flash has a maximum clock rate of 80 MHz. The Bambino 200 uses a 4M flash and the Bambino 200E uses an 8M flash. Both memories have 4KB sectors.
USB Power Mux
Texas Instruments TPS2115 auto-switching power mux is used to select between USB0 and USB1. It provides a seamless transition between USB1 and USB0 on the Bambino 200. The TPS2115 includes thermal protection and reverse-conduction blocking.
Ethernet PHY (Bambino 200E)
The Bambino 200E includes a Micrel KSZ8081 10 Base-T/100 Base-TX Physical Layer Transceiver (PHY). The PHY has a RMII interface to transmit and receive data to the LPC4330's Media Access Controller. It has auto-negotiation to automatically select the highest link-up speed (10/100 Mbps) and duplex (half/full). For further information please see KSZ8081 Data Sheet.