Bambino Family of Controllers

The Micromint Bambino 100 is a multi-core SBC designed for compatibility with microPython or the mbed framework. microPython is an implementation of Python 3 that has been optimized to run on a microcontroller. It allows for quick and easy programs to integrate systems faster. The mbed framework is a popular framework for embedded software development that includes extensive class libraries, tools and broad community support, allowing you to deliver embedded applications faster and more reliably. The Micromint Bambino 100 is powered by an NXP LPC4337, the first dual-core ARM Cortex-M microcontroller. Its Cortex-M4 and Cortex-M0 cores are both capable of concurrent 204 MHz operation. The hardware block diagram and feature summary is included below:

Bambino 100 Base Features

• 204 MHz Dual Core 32-bit ARMŽ Cortex?-M4/M0
• 1MB of Flash
• 136k of SRAM
• 16k of EEPROM
• 2 USB Device Port
• 2 Push Buttons
• 4 LEDs
• microSD Socket
• 32 GPIO

Bambino 100 Optional Features

• MBED HDK/CMSIS DAP
• ESP12 WiFi Module
• 8M SPIFI Flash

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The following image shows where some of the hardware components are located.

Microcontroller

The Bambino 100 includes a NXP LPC4337 microcontroller. These dual core 32-bit ARM Cortex-M4/M0 RISC microcontroller are capable of 204-MHz operation with a Thumb2 instruction set for smaller object code. It uses a Harvard architecture with separate local instruction and data buses as well as a separate peripherals bus. Please see NXP?s LPC4337 Microcontroller's User Manual for more information and register definitions.

LPC4337 key features

• Cortex-M4 Processor core
  • ARM Cortex-M4 processor (version r0p1), running at frequencies of up to 204 MHz.
  • Built-in Memory Protection Unit (MPU) supporting eight regions.
  • Built-in Nested Vectored Interrupt Controller (NVIC).
  • Hardware floating-point unit.
  • Non-maskable Interrupt (NMI) input.
  • JTAG and Serial Wire Debug (SWD), serial trace, eight breakpoints, and four watch points.
  • Enhanced Trace Module (ETM) and Enhanced Trace Buffer (ETB) support.
  • System tick timer.
• Cortex-M0 Processor core
  • ARM Cortex-M0 co-processor (version r0p0) capable of off-loading the main ARM Cortex-M4 application processor.
  • Running at frequencies of up to 204 MHz.
  • JTAG
  • Built-in NVIC.
• On-chip memory
  • Up to 1 MB on-chip dual bank flash memory with flash accelerator.
  • 16 kB on-chip EEPROM data memory.
  • 136 kB SRAM for code and data use.
  • Multiple SRAM blocks with separate bus access. Two SRAM blocks can be powered down individually.
  • 64 kB ROM containing boot code and on-chip software drivers.
  • 64 bit+ 256 bit of One-Time Programmable (OTP) memory for general-purpose use.
• Configurable digital peripherals
  • Serial GPIO (SGPIO) interface.
  • State Configurable Timer (SCTimer/PWM) subsystem on AHB.
  • Global Input Multiplexer Array (GIMA) allows to cross-connect multiple inputs and outputs to event driven peripherals like the timers, SCTimer/PWM, and ADC0/1.
• Serial interfaces
  • Quad SPI Flash Interface (SPIFI) with four lanes and up to 52 MB per second.
  • 10/100T Ethernet MAC with RMII and MII interfaces and DMA support for high throughput at low CPU load. Support for IEEE 1588 time stamping/advanced time stamping (IEEE 1588-2008 v2).
  • One High-speed USB 2.0 Host/Device/OTG interface with DMA support and on-chip high-speed PHY.
  • One High-speed USB 2.0 Host/Device interface with DMA support, on-chip full-speed PHY and ULPI interface to external high-speed PHY.
  • USB interface electrical test software included in ROM USB stack.
  • One 550 UART with DMA support and full modem interface.
  • Three 550 USARTs with DMA and synchronous mode support and a smart card interface conforming to ISO7816 specification. One USART with IrDA interface.
  • Up to two C_CAN 2.0B controllers with one channel each.
  • Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMA support.
  • One SPI controller.
  • One Fast-mode Plus I2C-bus interface with monitor mode and with open-drain I/O pins conforming to the full I2C-bus specification. Supports data rates of up to 1 Mbit/s.
  • One standard I2C-bus interface with monitor mode and with standard I/O pins.
  • Two I2S interfaces, each with DMA support and with one input and one output.
• Digital peripherals
  • External Memory Controller (EMC) supporting external SRAM, ROM, NOR flash, and SDRAM devices.
  • Secure Digital Input Output (SD/MMC) card interface.
  • Eight-channel General-Purpose DMA controller can access all memories on the AHB and all DMA-capable AHB slaves.
  • Up to 164 General-Purpose Input/Output (GPIO) pins with configurable pull-up/pull-down resistors.
  • GPIO registers are located on the AHB for fast access. GPIO ports have DMA support.
  • Up to eight GPIO pins can be selected from all GPIO pins as edge and level sensitive interrupt sources.
  • Two GPIO group interrupt modules enable an interrupt based on a programmable pattern of input states of a group of GPIO pins.
  • Four general-purpose timer/counters with capture and match capabilities.
  • One motor control Pulse Width Modulator (PWM) for three-phase motor control.
  • One Quadrature Encoder Interface (QEI).
  • Repetitive Interrupt timer (RI timer).
  • Windowed watchdog timer (WWDT).
  • Ultra-low power Real-Time Clock (RTC) on separate power domain with 256 bytes of battery powered backup registers.
  • Alarm timer; can be battery powered.
• Analog peripherals
  • One 10-bit DAC with DMA support and a data conversion rate of 400 kSamples/s.
  • Two 10-bit ADCs with DMA support and a data conversion rate of 400 kSamples/s. Up to eight input channels per ADC.
• Unique ID for each device.
• Clock generation unit
  • Crystal oscillator with an operating range of 1 MHz to 25 MHz.
  • 12 MHz internal RC oscillator trimmed to 3 % accuracy over temperature and voltage (1.5 % accuracy for Tamb = 0 °C to 85 °C).
  • Ultra-low power Real-Time Clock (RTC) crystal oscillator.
  • Three PLLs allow CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. The second PLL can be used with the High-speed USB, the third PLL can be used as audio PLL.
  • Clock output.
• Power
  • Single 3.3 V (2.4 V to 3.6 V) power supply with on-chip DC-to-DC converter for the core supply and the RTC power domain.
  • RTC power domain can be powered separately by a 3 V battery supply.
  • Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down.
  • Processor wake-up from Sleep mode via wake-up interrupts from various peripherals. Wake-up from Deep-sleep, Power-down, and Deep power-down modes via external interrupts and interrupts generated by battery powered blocks in the RTC power domain.
  • Brownout detect with four separate thresholds for interrupt and forced reset.
  • Power-On Reset (POR).

LPC4337 Block Diagram

LPC4337 Block Diagram

LPC4337 Memory Map

LPC4337 Memory Map

ESP12 WiFi Module Option

The ESP12 is a WiFi module based on the ESP8266 processor from Espressif. It is a microcontroller with a WiFi front-end and TCP/IP stack with DNS support. The ESP12 can be populated on the bottom of the Bambino 100.

MBED HDK Option

The MBED HDK is powered by NXP's LPC11U35. The mbed HDK uses the CMSIS-DAP Interface design that provides simple USB drag-n-drop programming and CMSIS-DAP debug interface for the target microcontroller.

Serial Flash Memory Option

The Bambino 100 has an optional Quad SPI Flash for program and non-volatile data storage. The quad SPI flash has a maximum clock rate of 80 MHz.

NEXT: User Interfaces, Connectors, and Jumpers

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The following image shows where the connectors, headers, and jumpers are located on the Bambino 100.

Bambino 100 Module Pin Out

The Bambino 100's module pin out. The headers use 0.1 inch spacing between pins.

Onboard Peripherals

USB0 Device

The Bambino 100 comes equipped with a USB Device Port. The Device port is compliant with the USB V2.0 high-speed device specification. It's connector is a micro USB Type AB.

Boot Jumper

The boot jumper is used to put the Bambino 100 into Device Firmware Upgrade (DFU) mode. This is accomplished by shorting the two pins before power is applied or by shorting the pins and pressing the reset button. For further information please see the Getting Started Section of this manual.

User Buttons and LEDs

The Bambino 100 comes standard with a user push button, a reset push button, and four user LEDs. The user push button is connected to GPIO0[7] with a 22k-ohm pull-up resistor connected to it. User LED1 (yellow) can be illuminated by clearing GPIO3[7] of the LPC4337. User LED2 (green) can be illuminated by clearing GPIO5[5]. User LED3 (blue) can be illuminated by clearing GPIO3[0]. User LED4 (red) can be illuminated by clearing GPIO3[1].

MICRO SD

The microSD socket (J2) enables micro-secure-digital memory cards to be plugged into the Bambino 100 microcontroller board. The microSD card allows the user the ability of a standard removable media for transferring data to and from the Bambino 100. The LPC4337 interfaces to the microSD card through the Secure Digital Input Output card interface.

ESP12 WiFi (Optional)

The ESP12 WiFi Module adds wireless support to the Bambino 100.

MBED HDK/CMSIS DAP (Optional)

The Bambino 100 optionally comes equipped with the MBED HDK. It is powered by NXP's LPC11U35 microcontroller. The MBED HDK is compliant with the USB V2.0 full-speed device specification. It's connector is a micro USB Type AB and is designated J6.

MBED HDK/CDC Device (Optional)

The MBED HDK implements a virtual serial port via USB using I/O from UART2 in the LPC4337. This allows simple serial I/O from mbed applications to terminal emulators such as PuTTY.

Serial Flash Memory (Optional)

The Bambino 100 has an option to populate serial flash for program and nonvolatile data storage. It uses the LPC4337's Quad SPI Flash Iinterface (SPIFI). The SPIFI interface has data rates up to 52 MB per second.

NEXT: Mechanical and Electrical Characteristics

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