Bambino-200 Manual/Hardware - Revision history

Support at 13:05, 11 March 2014

2014-03-11T13:05:16Z

← Older revision		Revision as of 13:05, 11 March 2014
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	==Serial Flash Memory==		==Serial Flash Memory==
	The Bambino 200 uses Quad SPI Flash for it's program and non-volatile data storage. The quad SPI flash has a maximum clock rate of 80 MHz. The Bambino 200 uses a 4M flash and the Bambino 200E uses an 8M flash. Both memories have 4KB sectors.		The Bambino 200 uses Quad SPI Flash for it's program and non-volatile data storage. The quad SPI flash has a maximum clock rate of 80 MHz. The Bambino 200 uses a 4M flash and the Bambino 200E uses an 8M flash. Both memories have 4KB sectors.
		+
		+	==USB Power Mux==
		+	Texas Instruments TPS2115 auto-switching power mux is used to select between USB0 and USB1. It provides a seamless transition between USB1 and USB0 on the Bambino 200. The TPS2115 includes thermal protection and reverse-conduction blocking.

	==Ethernet PHY (Bambino 200E)==		==Ethernet PHY (Bambino 200E)==
-	The Bambino 200E includes a Micrel ~~KSZ8031~~ 10 Base-T/100 Base-TX Physical Layer Transceiver (PHY). The PHY has a RMII interface to transmit and receive data to the LPC4330's Media Access Controller. It has auto-negotiation to automatically select the highest link-up speed (10/100 Mbps) and duplex (half/full). For further information please see ~~KSZ8031~~ Data Sheet.	+	The Bambino 200E includes a Micrel KSZ8081 10 Base-T/100 Base-TX Physical Layer Transceiver (PHY). The PHY has a RMII interface to transmit and receive data to the LPC4330's Media Access Controller. It has auto-negotiation to automatically select the highest link-up speed (10/100 Mbps) and duplex (half/full). For further information please see KSZ8081 Data Sheet.

Support: /* Serial Flash Memory */

2014-02-04T21:49:32Z

Serial Flash Memory

← Older revision		Revision as of 21:49, 4 February 2014
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	==Serial Flash Memory==		==Serial Flash Memory==
-	The Bambino ~~210~~ uses Quad SPI Flash for it's program and non-volatile data storage. The quad SPI flash has a maximum clock rate of 80 MHz. The Bambino ~~210~~ uses a 4M flash and the Bambino 200E uses an 8M flash. Both memories have 4KB sectors.	+	The Bambino 200 uses Quad SPI Flash for it's program and non-volatile data storage. The quad SPI flash has a maximum clock rate of 80 MHz. The Bambino 200 uses a 4M flash and the Bambino 200E uses an 8M flash. Both memories have 4KB sectors.

	==Ethernet PHY (Bambino 200E)==		==Ethernet PHY (Bambino 200E)==

Support: /* Serial Flash Memory */

2014-02-04T21:49:06Z

Serial Flash Memory

← Older revision		Revision as of 21:49, 4 February 2014
Line 85:		Line 85:

	==Serial Flash Memory==		==Serial Flash Memory==
-	The Bambino ~~200~~ uses Quad SPI Flash for it's program and non-volatile data storage. The quad SPI flash has a maximum clock rate of 80 MHz. The Bambino ~~200~~ uses a 4M flash and the Bambino 200E uses an 8M flash. Both memories have 4KB sectors.	+	The Bambino 210 uses Quad SPI Flash for it's program and non-volatile data storage. The quad SPI flash has a maximum clock rate of 80 MHz. The Bambino 210 uses a 4M flash and the Bambino 200E uses an 8M flash. Both memories have 4KB sectors.

	==Ethernet PHY (Bambino 200E)==		==Ethernet PHY (Bambino 200E)==

Support at 18:45, 1 February 2014

2014-02-01T18:45:39Z

← Older revision		Revision as of 18:45, 1 February 2014
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	===LPC4330 Block Diagram===		===LPC4330 Block Diagram===
-	[[Image:Bambino-200-MCUBlock.png\|center\|alt=~~Bambino 200~~\|frame\|<div align="center">'''LPC4330 Block Diagram]]	+	[[Image:Bambino-200-MCUBlock.png\|center\|alt=LPC4330 Block Diagram\|frame\|<div align="center">'''LPC4330 Block Diagram]]
	</div>		</div>

	===LPC4330 Memory Map===		===LPC4330 Memory Map===
-	[[Image:Bambino-200-Mem-Map.png\|center\|alt=~~Bambino 200~~\|frame\|<div align="center">'''LPC4330 Memory Map]]	+	[[Image:Bambino-200-Mem-Map.png\|center\|alt=LPC4330 Memory Map\|frame\|<div align="center">'''LPC4330 Memory Map]]
	</div>		</div>

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	The Bambino 200 uses Quad SPI Flash for it's program and non-volatile data storage. The quad SPI flash has a maximum clock rate of 80 MHz. The Bambino 200 uses a 4M flash and the Bambino 200E uses an 8M flash. Both memories have 4KB sectors.		The Bambino 200 uses Quad SPI Flash for it's program and non-volatile data storage. The quad SPI flash has a maximum clock rate of 80 MHz. The Bambino 200 uses a 4M flash and the Bambino 200E uses an 8M flash. Both memories have 4KB sectors.

-	==PHY (Bambino 200E)==	+	==Ethernet PHY (Bambino 200E)==
	The Bambino 200E includes a Micrel KSZ8031 10 Base-T/100 Base-TX Physical Layer Transceiver (PHY). The PHY has a RMII interface to transmit and receive data to the LPC4330's Media Access Controller. It has auto-negotiation to automatically select the highest link-up speed (10/100 Mbps) and duplex (half/full). For further information please see KSZ8031 Data Sheet.		The Bambino 200E includes a Micrel KSZ8031 10 Base-T/100 Base-TX Physical Layer Transceiver (PHY). The PHY has a RMII interface to transmit and receive data to the LPC4330's Media Access Controller. It has auto-negotiation to automatically select the highest link-up speed (10/100 Mbps) and duplex (half/full). For further information please see KSZ8031 Data Sheet.

Support at 11:24, 11 July 2013

2013-07-11T11:24:16Z

← Older revision		Revision as of 11:24, 11 July 2013
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-	[[Category: Bambino-200_Manual\|7]]	+	[[Category: Bambino-200_Manual\|07]]
	The following image shows where some of the hardware components are located.		The following image shows where some of the hardware components are located.

Support at 04:56, 8 July 2013

2013-07-08T04:56:28Z

← Older revision		Revision as of 04:56, 8 July 2013
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-	[[Category: Bambino-200_Manual\|5]]	+	[[Category: Bambino-200_Manual\|7]]
	The following image shows where some of the hardware components are located.		The following image shows where some of the hardware components are located.

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	[[Bambino-200_Manual/User Interfaces, Connectors, and Jumpers\|NEXT: User Interfaces, Connectors, and Jumpers]]		[[Bambino-200_Manual/User Interfaces, Connectors, and Jumpers\|NEXT: User Interfaces, Connectors, and Jumpers]]

-	[[Bambino-200_Manual/~~Updating~~ Firmware\|PREVIOUS: ~~Updating~~ Firmware]]	+	[[Bambino-200_Manual/Rebuild mbed Firmware\|PREVIOUS: Rebuild mbed Firmware]]

Support at 04:55, 26 June 2013

2013-06-26T04:55:15Z

← Older revision		Revision as of 04:55, 26 June 2013
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-	[[Category: Bambino-200_Manual\|3]]	+	[[Category: Bambino-200_Manual\|5]]
	The following image shows where some of the hardware components are located.		The following image shows where some of the hardware components are located.

Support: /* PHY (Bambino 200E) */

2013-06-26T03:43:37Z

PHY (Bambino 200E)

← Older revision		Revision as of 03:43, 26 June 2013
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	[[Bambino-200_Manual/User Interfaces, Connectors, and Jumpers\|NEXT: User Interfaces, Connectors, and Jumpers]]		[[Bambino-200_Manual/User Interfaces, Connectors, and Jumpers\|NEXT: User Interfaces, Connectors, and Jumpers]]

-	[[Bambino-200_Manual/~~Getting_Started~~\|PREVIOUS: ~~Getting Started~~]]	+	[[Bambino-200_Manual/Updating Firmware\|PREVIOUS: Updating Firmware]]

Support: /* Microcontroller */

2013-06-13T18:31:53Z

Microcontroller

← Older revision		Revision as of 18:31, 13 June 2013
Line 7:		Line 7:
	The Bambino 200 includes a NXP LPC4330 microcontroller. These dual core 32-bit ARM Cortex-M4/M0 RISC microcontroller are capable of 204-MHz operation with a Thumb2 instruction set for smaller object code. It uses a Harvard architecture with separate local instruction and data buses as well as a separate peripherals bus. Please see NXP’s LPC4330 Microcontroller's User Manual for more information and register definitions.		The Bambino 200 includes a NXP LPC4330 microcontroller. These dual core 32-bit ARM Cortex-M4/M0 RISC microcontroller are capable of 204-MHz operation with a Thumb2 instruction set for smaller object code. It uses a Harvard architecture with separate local instruction and data buses as well as a separate peripherals bus. Please see NXP’s LPC4330 Microcontroller's User Manual for more information and register definitions.

-	===~~'''~~LPC4330 key features~~:'''~~===	+	===LPC4330 key features===
	*Cortex-M4 Processor core		*Cortex-M4 Processor core
	**Built-in Memory Protection Unit (MPU) supporting eight regions.		**Built-in Memory Protection Unit (MPU) supporting eight regions.
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	**Power-On Reset (POR).		**Power-On Reset (POR).

		+	===LPC4330 Block Diagram===
	[[Image:Bambino-200-MCUBlock.png\|center\|alt=Bambino 200\|frame\|<div align="center">'''LPC4330 Block Diagram]]		[[Image:Bambino-200-MCUBlock.png\|center\|alt=Bambino 200\|frame\|<div align="center">'''LPC4330 Block Diagram]]
	</div>		</div>

-		+	===LPC4330 Memory Map===
	[[Image:Bambino-200-Mem-Map.png\|center\|alt=Bambino 200\|frame\|<div align="center">'''LPC4330 Memory Map]]		[[Image:Bambino-200-Mem-Map.png\|center\|alt=Bambino 200\|frame\|<div align="center">'''LPC4330 Memory Map]]
	</div>		</div>

Support: /* Microcontroller */

2013-06-13T18:29:40Z

Microcontroller

← Older revision		Revision as of 18:29, 13 June 2013
Line 7:		Line 7:
	The Bambino 200 includes a NXP LPC4330 microcontroller. These dual core 32-bit ARM Cortex-M4/M0 RISC microcontroller are capable of 204-MHz operation with a Thumb2 instruction set for smaller object code. It uses a Harvard architecture with separate local instruction and data buses as well as a separate peripherals bus. Please see NXP’s LPC4330 Microcontroller's User Manual for more information and register definitions.		The Bambino 200 includes a NXP LPC4330 microcontroller. These dual core 32-bit ARM Cortex-M4/M0 RISC microcontroller are capable of 204-MHz operation with a Thumb2 instruction set for smaller object code. It uses a Harvard architecture with separate local instruction and data buses as well as a separate peripherals bus. Please see NXP’s LPC4330 Microcontroller's User Manual for more information and register definitions.

-	'''LPC4330 key features:'''	+	==='''LPC4330 key features:'''===
	*Cortex-M4 Processor core		*Cortex-M4 Processor core
	**Built-in Memory Protection Unit (MPU) supporting eight regions.		**Built-in Memory Protection Unit (MPU) supporting eight regions.